module prescaler(
    input inclk,
    input RESETn,
    output reg outclk
);
    reg [3:0] count;

    always @(posedge inclk or negedge RESETn) begin
        if (!RESETn) begin
            count <= 4'b0000;
            outclk <= 0;     
        end else begin
            if (count == 4'b1111) begin
                outclk <= ~outclk; 
                count <= 4'b0000;  
            end else begin
                count <= count + 1;
            end
        end
    end

endmodule
